A wafer level chip scale package (WLCSP) is a small integrated circuit (IC) package typically used in mobile phones, personal digital assistants (PDA's), notebook computers, printers, and similar devices. A WLCSP usually has an area no greater than 1.2 times that of the IC die. It is a single-die, direct surface mountable package that may be secured to a printed circuit board (PCB) by conventional surface mount technology. The pads of the IC die connect to pads of the PCB through individual solder balls that typically require no underfill encapsulation and typically require no bond wires between the IC die and solder balls. This reduces the inductance between the IC die and the PCB and improves signal quality. The ball pitch is usually no more than 1 millimeter (mm). Pads are etched or printed directly onto the silicon wafer, resulting in a semiconductor package close to the size of the IC die. For that reason, it is given the name wafer level chip scale package.
Some WLCSP's are direct-bump designs, where the solder balls are placed directly above a bond pad on the die. Many WLCSP's, however, use a redistribution layer (RDL) as a copper or other metal interconnect layer applied after repassivation to route original bond pads to new solder ball locations that are not directly above the original bond pads. In RDL technology, the bare silicon wafer is repassivated with a polymer dielectric layer, but the original bond pads are left exposed. A copper redistribution layer is applied after repassivation to route the original bond pads to the new solder ball locations. A second polymer passivation or dielectric layer isolates the copper RDL layer. The die are singulated, i.e., cut, after the solder balls are placed.
A wafer level chip scale package typically includes a back end of line (BEOL) layer on the semiconductor substrate that is applied during a latter or “back end” part of the IC fabrication. Individual devices, including transistors, capacitors and resistors, are interconnected on the wafer. The BEOL layer includes contacts, insulating layers (dielectrics), metal levels, and bonding sites. As many as 3 to 10 layers may be added to form the BEOL layer. This is followed by applying passivation, first dielectric, RDL, and second dielectric layers. The repassivation layer and dielectric layers impart tensile stress at the edge of the BEOL layer, creating a risk of delamination near that edge. This results in device failure. It may be desirable to increase reliability by lowering the tensile stress at the edge of the BEOL layer.